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library ieee;
use IEEE.STD_LOGIC_1164.ALL;

entity F1 is 
	Port(	x1 : in STD_LOGIC;
			x2 : in STD_LOGIC;
			x3 : in STD_LOGIC;
			x4 : in STD_LOGIC;
			y  : out STD_LOGIC);
end F1;

architecture SIEC of F1 is

	component NOT1 is
		Port(
			a : in STD_LOGIC;
		    z : out STD_LOGIC
			);
	end component NOT1;

	component NAND3 is 
		Port(	
			a,b,c : in STD_LOGIC;
			z	  : out STD_LOGIC
			);
	end component NAND3;

	component NAND2 is
		Port( 	
			a,b : in STD_LOGIC;
			z 	: out STD_LOGIC
			);
	end component NAND2;

	signal nx1,nx2,nx3,nx4,v1,v2 : STD_LOGIC;
	
	begin 
		b1: NOT1  port map (x1, nx1); 
		b2: NOT1  port map (x2, nx2);
		b3: NOT1  port map (x3, nx3);
		b4: NOT1  port map (x4, nx4);
		b5: NAND3 port map (nx1, nx3, nx4, v1);
		b6: NAND3 port map (x1, nx3, x4, v2);
		b7: NAND2 port map (v1, v2, y);
	end SIEC;

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